TTTK 2833 - Assignment 2 (Question)

Answer all questions

1. In a computer, the clock cycle is the time between two adjacent pulses of the oscillator that sets the tempo of the computer processor. The number of these pulses per second is known as the clock speed, which is generally measured in MHz (megahertz, or millions of pulses per second) and lately even in GHz (gigahertz, or billions of pulses per second). The clock speed is determined by a quartz-crystal circuit, similar to those used in radio communications equipment.
a. Find a cycle time, in nanoseconds, for a 500MHz clock.
b. Find the clock frequency, in MHz, for a clock having a cycle of 10.5 ns

2. Word-addressable is a computer science term. In computer science, a word is an ordered set of bytes or bits (typically 2 bytes, or 16 bits) that is the normal unit in which information may be stored, transmitted, or operated on within a given computer. Typically, if a processor has a fixed-length instruction set, then the instruction length equals the word length.
a. Suppose a computer is word-addressable and main memory address is 21 bits in length. What is the size of the addressable memory?
b. Suppose a computer has a main memory of 512M words. What is the size, in bits of a main memory address?

3. A computer system has a main memory of 64K words where a word is a byte in length. It also has a 32 byte cache organization as 4 lines of 8 words. The cache mapping function is direct mapping function. The tags in the cache are currently:

Cache line - Tag

0-11011111010

1-00110001100

2-01010010111

3- 10001000111

a. How many bits in a main memory address?
b. When main memory is viewed as blocks, where a block is the size of the cache line, how many blocks are there in main memory?
c. When using a direct mapping function, a main memory address is viewed as consisting of 3 fields. For this machine, what is the size of each field in bits?
d. Each address is given in hexadecimal notation. Write the suitable tag, line and word for each of the following memory addresses:
i. 73B2
ii. DF45
iii. 8C7C
iv. 07E9
v. 318B

4. A set associative cache consists of 64 lines divided into four-line sets. Main memory consists of 4K blocks of 128 words each. Show the format of a main memory address.

5. A microprocessor has a 32-bit word size and a 16KB 4-way set associative cache where each cache line holds four words. If we assume that the machine is byte-addressable, the word field for this problem is 4 bits. Since a word is 4 bytes and there are 4 words per cache line, the most-significant 2 bits selects one of the four words in the line and the least significant 2 bits selects one of the four bytes within the word.
a. If a main memory address is 32 bits, what is the format of a main memory address?
b. Where in the cache is the word from memory location 3A2C6F0D mapped?