Answer
1. (a) 1 / 500 mhz = 1sec / 500 x 106 cycles = 2 x 10-9 sec per cycle = 2ns per cycle
(b) 1 / 10.5 ns = 1cycle / 10.5 x 10-9 sec = 0.9524 x 108 cycles per sec = 95.24 x 106= 95.24 MHz
2. (a) 221 = 2 1 x 220 = 2048 KWords
(b) 512 M = 2 56 , Main memory address is 56 bits.
3. (a) 64K = 216, 16 bits in a main memory address.
(b) A memory block is equal to 8 words, and 216 ÷ 23 = 216-3 = 213. Then is 213 = 8K blocks in
main memory.
(c)
Tag | Line | Word |
11 | 2 | 3 |
(d)
| Tag | Line | Word | |
i. 73B2 | 01110011101 | 10 | 010 | line 2 word 2 |
ii. DF45 | 11011111010 | 00 | 101 | line 0 word 5 |
iii. 8C7C | 10001100011 | 11 | 100 | line 3 word 4 |
iv. 07E9 | 00000111111 | 01 | 001 | line 1 word 1 |
v. 318B | 00110001100 | 01 | 011 | line 1 word 3 |
4. The Main memory is 128 × 4K words = 27x 212 = 219 words. Means main memory address is 19 bits long. A cache line is the size of a memory block, then a cache line is 128 = 27 words and the word field is 7 bits. If there are 64 cache lines is divided into 4 line sets, then is 64 ÷ 4 = 16 sets. The set field is 4 bits. This leaves 8 bits for the tag field.
Tag | Line | Word |
8 | 4 | 7 |
5. (a) The word = 4 bits. Each cache line = 16 bytes: a line = 4 words; a word = 4 bytes.
The cache is 4-way set associative, 4 lines to aset. Then a set is 4 lines × 16 bytes per line = 64 bytes, and 16KB ÷ 64 bytes = 214 ÷ 26 = 28 sets. The set field, therefore is 8 bits. The main
memory address is 32 bits ,then the tag field is 32 - (8 + 4) = 20 bits.
Tag | Line | Word |
20 | 8 | 4 |
6 (b)
3 | A | 2 | C | 6 | F | 0 | D |
0011 | 1010 | 0010 | 1100 | 0110 | 1111 | 0000 | 1101 |
Word: 1101b = 13d = Dh. If tmachine is byte-addressable, means byte 1 from word 3.
Set: 11110000 = 240d = F0h
Tag: 00111010001011000110b = 238278d = 3A2C6h
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