TTTK2163 Assignment 2- Regular Expression (Redo Answer)

TTTK 2833 - Assignment 3 (Solution Manual) By R8y™

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TTTK 2833 - Computer Organization and Architecture: Designing for Performance Book

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TTTK2163 - COMPILERS BOOK

TTTK 2833 - Assignment 3 (Question)

Assignment 3 (Individual Assignment)
Due on 11th February 2010

1. List then briefly explain five important instruction set design issues.

2. What is the difference between big endian and little endian?

3. What is the difference between an arithmetic shift and a logical shift?

4. Briefly define the followings:
a. Immediate addressing
b. Direct addressing
c. Indirect addressing
d. Register addressing
e. Register indirect addressing
f. Displacement addressing
g. Relative addressing

5. Consider a 16-bit processor in which the following appears in main memory, starting at location 200:
200 Load to AC Mode
201 500
202 Next instruction
The first part of the first word indicates that this instruction loads a value into an accumulator. The Mode field specifies an addressing mode and, if appropriate, indicates a source register; assuming that when used, the source register is R1, which has a value of 400. There is also a base register that contains the value of 100. the value of 500 in location 201 may be part of the address calculation. Assume that location 399 contains the value 999, location 400 contains the value 1000, and so on.
Determine the effective address and the operand to be loaded for the following addressing modes:
a. Direct
b. Immediate
c. Indirect
d. Displacement
e. Register
f. Register indirect

6. Assume a stack-oriented processor that includes the stack operations PUSH and POP. Arithmetic operations automatically involve the top one or two stack elements. Begin with an empty stack. Show the stack elements after execution of each instruction.
PUSH 2
PUSH 5
PUSH 4
ADD
PUSH 8
ADD
MUL

TTTK2163 Assignment 2- Regular Expression (Answer)

TTTK 2833 - Assignment 2 (Answer)

Answer

1. (a) 1 / 500 mhz = 1sec / 500 x 10⁶ cycles = 2 x 10^-9 sec per cycle = 2ns per cycle

(b) 1 / 10.5 ns = 1cycle / 10.5 x 10^-9 sec = 0.9524 x 10⁸ cycles per sec = 95.24 x 10⁶= 95.24 MHz

2. (a) 221 = 2 ¹ x 2²⁰ = 2048 KWords

(b) 512 M = 2 ⁵⁶ , Main memory address is 56 bits.

3. (a) 64K = 2¹⁶, 16 bits in a main memory address.

(b) A memory block is equal to 8 words, and 216 ÷ 23 = 216-3 = 213. Then is 213 = 8K blocks in

main memory.

(c)

Tag	Line	Word
11	2	3

(d)

	Tag	Line	Word
i. 73B2	01110011101	10	010	line 2 word 2
ii. DF45	11011111010	00	101	line 0 word 5
iii. 8C7C	10001100011	11	100	line 3 word 4
iv. 07E9	00000111111	01	001	line 1 word 1
v. 318B	00110001100	01	011	line 1 word 3

4. The Main memory is 128 × 4K words = 2⁷x 2¹² = 2¹⁹ words. Means main memory address is 19 bits long. A cache line is the size of a memory block, then a cache line is 128 = 27 words and the word field is 7 bits. If there are 64 cache lines is divided into 4 line sets, then is 64 ÷ 4 = 16 sets. The set field is 4 bits. This leaves 8 bits for the tag field.

Tag	Line	Word
8	4	7

5. (a) The word = 4 bits. Each cache line = 16 bytes: a line = 4 words; a word = 4 bytes.

The cache is 4-way set associative, 4 lines to aset. Then a set is 4 lines × 16 bytes per line = 64 bytes, and 16KB ÷ 64 bytes = 2¹⁴ ÷ 2⁶ = 2⁸ sets. The set field, therefore is 8 bits. The main

memory address is 32 bits ,then the tag field is 32 - (8 + 4) = 20 bits.

Tag	Line	Word
20	8	4

6 (b)

3	A	2	C	6	F	0	D
0011	1010	0010	1100	0110	1111	0000	1101

Word: 1101b = 13d = Dh. If tmachine is byte-addressable, means byte 1 from word 3.

Set: 11110000 = 240d = F0h

Tag: 00111010001011000110b = 238278d = 3A2C6h

TTTK 2833 - Assignment 2 (Question)

Answer all questions

1. In a computer, the clock cycle is the time between two adjacent pulses of the oscillator that sets the tempo of the computer processor. The number of these pulses per second is known as the clock speed, which is generally measured in MHz (megahertz, or millions of pulses per second) and lately even in GHz (gigahertz, or billions of pulses per second). The clock speed is determined by a quartz-crystal circuit, similar to those used in radio communications equipment.
a. Find a cycle time, in nanoseconds, for a 500MHz clock.
b. Find the clock frequency, in MHz, for a clock having a cycle of 10.5 ns

2. Word-addressable is a computer science term. In computer science, a word is an ordered set of bytes or bits (typically 2 bytes, or 16 bits) that is the normal unit in which information may be stored, transmitted, or operated on within a given computer. Typically, if a processor has a fixed-length instruction set, then the instruction length equals the word length.
a. Suppose a computer is word-addressable and main memory address is 21 bits in length. What is the size of the addressable memory?
b. Suppose a computer has a main memory of 512M words. What is the size, in bits of a main memory address?

3. A computer system has a main memory of 64K words where a word is a byte in length. It also has a 32 byte cache organization as 4 lines of 8 words. The cache mapping function is direct mapping function. The tags in the cache are currently:

Cache line - Tag

0-11011111010

1-00110001100

2-01010010111

3- 10001000111

a. How many bits in a main memory address?
b. When main memory is viewed as blocks, where a block is the size of the cache line, how many blocks are there in main memory?
c. When using a direct mapping function, a main memory address is viewed as consisting of 3 fields. For this machine, what is the size of each field in bits?
d. Each address is given in hexadecimal notation. Write the suitable tag, line and word for each of the following memory addresses:
i. 73B2
ii. DF45
iii. 8C7C
iv. 07E9
v. 318B

4. A set associative cache consists of 64 lines divided into four-line sets. Main memory consists of 4K blocks of 128 words each. Show the format of a main memory address.

5. A microprocessor has a 32-bit word size and a 16KB 4-way set associative cache where each cache line holds four words. If we assume that the machine is byte-addressable, the word field for this problem is 4 bits. Since a word is 4 bytes and there are 4 words per cache line, the most-significant 2 bits selects one of the four words in the line and the least significant 2 bits selects one of the four bytes within the word.
a. If a main memory address is 32 bits, what is the format of a main memory address?
b. Where in the cache is the word from memory location 3A2C6F0D mapped?