TTTK 2833 - Assignment 4 (Answer)

TTTK 2833 - Assignment 4 (Question)

Assignment 4 ( File System )
Due on 25/3/2010

Please show all work on a separate sheet attached to this sheet.
1. What is a file descriptor?

2. What are the file descriptors for stdin, stdout, and stderr, respectively.

3. What functions are used to duplicate a file descriptor?

4. What is a block special file? Give an example of a block special file.

5. What is a character special file? Give an example of a character special file.

6. What is the essential difference between a block special file and a character file?

7. Consider a disk with a mean seek time of 9.4 msec, a rotational rate of 7,500 rpm, and 524,288 bytes per tarck. What are the data rates for block siezes of 8 KB and 16 KB, respectively?

8. A file system checker has constructed the counters shown below:
 Block number 0 1 2 3 4 5 6 7 8 9
In use 1 0 0 2 1 0 1 0 1 1
Free 0 1 1 0 1 1 0 0 0 0

Are there any errors? If so, how serious are they (can they be fixed)? Explain.

9. The performance of a file system depends upon the cache hit rate (fraction of blocks found in the cache). If it takes 1 msec to satisfy a request from the cache, but 17 msec to satisfy a request if a disk read is needed:
a. Give a formula for the mean time required to satisfy a request if the hit rate is h.
b. What should the hit rate be to satisfy a request less than 9 msec?

10. What is the Distributed Denial of Service Attack?

TTTK 2833 - Assignment 3 (Solution Manual) By R8y™

Computer Organization and Architecture: Designing for Performance (Chapter 2 - 5 answer)

TTTK 2833 - Assignment 3 (Question)

Assignment 3 (Individual Assignment)
Due on 11th February 2010

1. List then briefly explain five important instruction set design issues.

2. What is the difference between big endian and little endian?

3. What is the difference between an arithmetic shift and a logical shift?

4. Briefly define the followings:
a. Immediate addressing
b. Direct addressing
c. Indirect addressing
d. Register addressing
e. Register indirect addressing
f. Displacement addressing
g. Relative addressing

5. Consider a 16-bit processor in which the following appears in main memory, starting at location 200:
200 Load to AC Mode
201 500
202 Next instruction
The first part of the first word indicates that this instruction loads a value into an accumulator. The Mode field specifies an addressing mode and, if appropriate, indicates a source register; assuming that when used, the source register is R1, which has a value of 400. There is also a base register that contains the value of 100. the value of 500 in location 201 may be part of the address calculation. Assume that location 399 contains the value 999, location 400 contains the value 1000, and so on.
Determine the effective address and the operand to be loaded for the following addressing modes:
a. Direct
b. Immediate
c. Indirect
d. Displacement
e. Register
f. Register indirect

6. Assume a stack-oriented processor that includes the stack operations PUSH and POP. Arithmetic operations automatically involve the top one or two stack elements. Begin with an empty stack. Show the stack elements after execution of each instruction.
PUSH 2
PUSH 5
PUSH 4
ADD
PUSH 8
ADD
MUL

TTTK 2833 - Assignment 2 (Answer)

Answer

1. (a) 1 / 500 mhz = 1sec / 500 x 10⁶ cycles = 2 x 10^-9 sec per cycle = 2ns per cycle

(b) 1 / 10.5 ns = 1cycle / 10.5 x 10^-9 sec = 0.9524 x 10⁸ cycles per sec = 95.24 x 10⁶= 95.24 MHz

2. (a) 221 = 2 ¹ x 2²⁰ = 2048 KWords

(b) 512 M = 2 ⁵⁶ , Main memory address is 56 bits.

3. (a) 64K = 2¹⁶, 16 bits in a main memory address.

(b) A memory block is equal to 8 words, and 216 ÷ 23 = 216-3 = 213. Then is 213 = 8K blocks in

main memory.

(c)

Tag	Line	Word
11	2	3

(d)

	Tag	Line	Word
i. 73B2	01110011101	10	010	line 2 word 2
ii. DF45	11011111010	00	101	line 0 word 5
iii. 8C7C	10001100011	11	100	line 3 word 4
iv. 07E9	00000111111	01	001	line 1 word 1
v. 318B	00110001100	01	011	line 1 word 3

4. The Main memory is 128 × 4K words = 2⁷x 2¹² = 2¹⁹ words. Means main memory address is 19 bits long. A cache line is the size of a memory block, then a cache line is 128 = 27 words and the word field is 7 bits. If there are 64 cache lines is divided into 4 line sets, then is 64 ÷ 4 = 16 sets. The set field is 4 bits. This leaves 8 bits for the tag field.

Tag	Line	Word
8	4	7

5. (a) The word = 4 bits. Each cache line = 16 bytes: a line = 4 words; a word = 4 bytes.

The cache is 4-way set associative, 4 lines to aset. Then a set is 4 lines × 16 bytes per line = 64 bytes, and 16KB ÷ 64 bytes = 2¹⁴ ÷ 2⁶ = 2⁸ sets. The set field, therefore is 8 bits. The main

memory address is 32 bits ,then the tag field is 32 - (8 + 4) = 20 bits.

Tag	Line	Word
20	8	4

6 (b)

3	A	2	C	6	F	0	D
0011	1010	0010	1100	0110	1111	0000	1101

Word: 1101b = 13d = Dh. If tmachine is byte-addressable, means byte 1 from word 3.

Set: 11110000 = 240d = F0h

Tag: 00111010001011000110b = 238278d = 3A2C6h